1. Field of the Invention
The present invention relates to formation of a contact opening in a dielectric layer to expose an active-device region of a semiconductor substrate. More particularly, the present invention relates to a method of removing a residual carbon/halide layer which forms in the contact opening during the etching of the dielectric layer or is intentionally deposited in the contact opening, wherein the removal of the carbon/halide layer also advantageously removes a damaged and/or dopant-depleted portion of the active-device region of the semiconductor substrate to expose a more highly-doped portion of the substrate upon which to form a contact.
2. State of the Art
In the processing of integrated circuits, electrical contact must be made to isolated active-device regions formed within a semiconductor substrate, such as a silicon wafer. Such active-device regions may include p-type and n-type source and drain regions used in the production of NMOS, PMOS, and CMOS structures for production of DRAM chips and the like. The active-device regions are connected by conductive paths or lines which are fabricated above an insulative or dielectric material covering a surface of the semiconductor substrate. To provide electrical connection between the conductive path and the active-device regions, openings in the insulative material are generally provided to enable a conductive material to contact the desired regions, thereby forming a "contact." The openings in the insulative material are typically referred to as "contact openings." Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. The advantages of increased miniaturization of components include: reduced-bulk electronic equipment, improved reliability by reducing the number of solder or plug connections, lower assembly and packaging costs, and improved circuit performance. In pursuit of increased miniaturization, semiconductor components have been continually redesigned to achieve ever higher degrees of integration which has reduced their size. However, as components become smaller and smaller, tolerances for all semiconductor structures (such as circuitry traces, contact openings, and the like) become more and more stringent. Moreover, the reduction in contact size (i.e., diameter) has resulted a small area of contact between the active-device regions and the conductive material of the contact. Regardless of the conductive material used to fill these small contact openings to form the contacts (such as tungsten, aluminum, or the like), the size reduction of the contact openings will demand effective removal of contaminants from the bottom of the contact opening to achieve efficient contact between the semiconductor substrate and the conductive material used to fill the contact opening.
By way of example, a widely-utilized DRAM (Dynamic Random Access Memory) manufacturing process utilizes CMOS (Complimentary Metal Oxide Semiconductor) technology to produce DRAM circuits which comprise an array of unit memory cells, each including one capacitor and one transistor, such as a field effect transistor ("FET"). A typical method for forming a contact opening for a CMOS FET is illustrated in FIGS. 7-11. It should be understood that the figures presented in conjunction with this description are not meant to be actual cross-sectional views of any particular portion of an actual semiconducting device, but are merely idealized representations which are employed to more clearly and fully depict the process of the invention than would otherwise be possible.
FIG. 7 illustrates an intermediate structure 200 in the production of a memory cell. This intermediate structure 200 comprises a semiconductor substrate 202, such as a lightly doped P-type silicon substrate, which has been oxidized to form thick field oxide areas 204 and exposed to dopant implantation processes to form active device regions 206, such as drain regions adjacent the field oxide areas 204 and source regions between the drain regions. Transistor gate members 212 are formed on the surface of the semiconductor substrate 202, including the gate members 212 residing on a substrate active area 210 spanned between the drain regions and the source regions. The transistor gate members 212 each comprise a lower buffer layer 214 separating a gate conducting layer or word line 216 of the transistor gate member 212 from the semiconductor substrate 202. Transistor insulating spacer members 218 are formed on either side of each transistor gate member 212 and a cap insulator 222 is formed on the top of each transistor gate member 212. A dielectric layer 224 is disposed over the semiconductor substrate 202, the thick field oxide areas 204, and the transistor gate members 212.
As shown in FIG. 8, a photoresist mask layer 226 is patterned on the dielectric layer 224, such that openings 228 (one illustrated) in the photoresist mask layer 226 is positioned over the active-device region 208 of the semiconductor substrate 202. The photoresist mask opening 228 is positioned over the source region for the formation of a contact opening for a bit line and positioned over the drain region for the formation of a contact opening for a capacitor. The materials used for the photoresist mask layer 226 are generally novolac resin photoresists, but may include halide-containing polymers, such as poly-trifluoroethyl chloroacrylate. Halides are compounds including at least one halogen element such as fluorine, chlorine, bromine, iodine, and astatine.
A contact opening 232 is etched through the opening 228 in the photoresist mask layer 226, as shown in FIG. 9. The etching may be performed by any known technique. However, a dry etch, such as plasma etching and reactive ion etching, is generally used for high aspect ratio etches in dielectric materials, such as silicon dioxide. Etchants used for forming the contact openings 232 also contain halide compounds, such as CF.sub.4, CHF.sub.3, C.sub.2 F.sub.6, CH.sub.2 F.sub.2, NF.sub.3, or other freons and mixtures thereof, in combination with a carrier gas, such as Ar, He, Ne, Kr, O.sub.2, N.sub.2, or a mixture thereof.
As a result of the etching process, a carbon/halide residue 234, usually a fluorocarbon residue, forms in the contact opening 232, as shown in FIG. 10. This carbon/halide residue 234 remains even after the photoresist mask layer 226 has been stripped away. The carbon/halide residue 234 is subsequently removed, usually with a plasma ashing technique using oxygen gas or oxygen gas with a halogen-containing gas, such as carbon tetrafluoride, as shown in FIG. 11. Although the plasma ashing and similar techniques efficiently remove the carbon/halide residue 234, the exposed portion 236 of the source region 208 proximate the contact opening 228 is usually reduced or depleted of dopant by the prior fabrication steps, such as dopant diffusing out of the source region 208 during thermal processing steps. The depletion of dopant results in the source region 208 being less conductive which, of course, reduces the efficiency of any subsequently formed contact.
Therefore, it would be desirable to develop a method for removing the carbon/halide residue from the contact openings while also removing a portion of the dopant-depleted active-device region in order to access more highly-doped, underlying portions of the active-device region for a more efficient contact.